1. Field of the Invention
The present invention relates to an output driver circuit, and more particularly to an output driver circuit which is capable of preventing an abrupt variation in the slew rate thereof when a variation in resistance and supply voltage occurs due to a variation in process and temperature conditions, so that it is widely usable on output stages of high-speed interface circuits.
2. Description of the Related Art
Semiconductor devices use an output driver circuit to output internal data from a chip thereof to the outside of the chip through an output terminal, that is, an output pad.
Such an output driver circuit includes a push-pull driver. One important function of such a push-pull driver is to control the slew rate of an output signal.
“Slew rate” means a variation rate of the voltage level of an output signal, so that it may be considered as a gradient of voltage to time. Such a slew rate may be a rising slew rate or a falling slew rate. The rising slew rate represents the gradient of an output voltage, the level of which is transited from a low level to a high level. On the other hand, the falling slew rate represents the gradient of an output voltage, the level of which is transited from a high level to a low level. At a higher slew rate, the gradient of the output voltage is sharper. In other words, the level of the output voltage is abruptly varied within a short time. Where an output push-pull driver exhibits a high slew rate, large noise current is generated. For this reason, such an output push-pull driver is unsuitable for the output stage of a high-speed interface circuit.
FIG. 1 illustrates a configuration of a conventional output driver circuit. Operation of the conventional driver circuit and problems involved therewith will be described with reference to FIG. 1.
FIG. 1 shows an example in which the conventional output driver circuit is applied to a DRAM. As shown in FIG. 1, the output driver circuit includes a pre-driver including a CMOS transistor composed of a PMOS transistor P1 and an NMOS transistor N1, and adapted to perform a switching operation in response to an input data signal IN, and another CMOS transistor composed of a PMOS transistor P2 and an NMOS transistor N2, and adapted to perform a switching operation in response to the input data signal IN. The output driver circuit also includes a PMOS transistor P0 serving as a pull-up element adapted to perform a switching operation in response to a signal at an output node up between the PMOS transistor P1 and the NMOS transistor N1, and an NMOS transistor N0 serving as a pull-down element adapted to perform a switching operation in response to a signal at an output node dn between the PMOS transistor P2 and the NMOS transistor N2.
The conventional output driver circuit further includes a means for controlling the slew rate of an output signal thereof. In the illustrated case, the slew rate control means comprises resistors R1 and R2 included in the pre-driver. In accordance with this configuration, when the input data signal IN has a high level, both the PMOS transistors P1 and P2 are turned off, whereas both the NMOS transistors N1 and N2 are turned on. In this state, discharging of current is carried out. As a result, the potential at the output node up, that is, voltage Vup, is lowered to a level Vss in accordance with a time constant t1 (t1=(R1+R_N1)×C_up). Here, “C_up” represents a parasitic capacitance generated at the output nod up, and “R_N1” represents an on-resistance of the NMOS transistor N1 in an ON state thereof. That is, the voltage Vup is lowered, as expressed by the following Expression:Vup=Vdd×e−t/t1  [Expression 1]
In accordance with Expression 1 associated with discharging of current, the PMOS transistor P0, which is a driving element, drives the voltage at an output terminal of the output driver circuit to a level Vdd. Thus, the resultant output signal has a certain slew rate.
Similarly, when the input data signal IN has a low level, both the NMOS transistors N1 and N2 are turned off, whereas both the PMOS transistors P1 and P2 are turned on. In this state, discharging of current is carried out. As a result, the potential at the output node dn, that is, voltage Vdn, is raised to the level Vdd in accordance with a time constant t2 (t2=(R2+R_P2)×C_dn). Here, “C_down” represents a parasitic capacitance generated at the output nod dn, and “R_P2” represents an on-resistance of the PMOS transistor P2 in an ON state thereof. That is, the voltage Vdn is raised, as expressed by the following Expression:Vdn=Vdd×(1−e−t/t2)  [Expression 2]
In accordance with the Expression associated with charging of current, the NMOS transistor N0, which is a driving element, drives the voltage at the output terminal of the output driver circuit to a level Vss. Thus, the resultant output signal has a certain slew rate.
However, the conventional output driver circuit has a problem in that the slew rate characteristics thereof are unstable. That is, the semiconductor memory device, to which the output driver circuit is applied, exhibits a high temperature variation during a process carried out thereby. In particular, the semiconductor memory device exhibits an increase in temperature during a high-speed operation thereof. In this case, the resistors included in the output driver circuit exhibit a variation in resistance because they are sensitive to a variation in temperature. For this reason, a variation in temperature causes each resistor to exhibit a variation in resistance, thereby varying the time constants t1 and t2, which are expressed in Expressions 1 and 2. As a result, respective voltages at the nodes up and dn vary. Thus; the conventional output driver circuit exhibits an abrupt variation in slew rate in accordance with a temperature variation occurring in the associated semiconductor memory device. Such a slew rate variation adversely affects the signal characteristics of the semiconductor memory device.